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Issue DateTitleAuthor(s)
1-May-1991EFFICIENT TECHNIQUES IN THE SIZING AND CONSTRAINED OPTIMIZATION OF CMOS COMBINATIONAL LOGIC-CIRCUITSHWANG, JS; WU, CY; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics
1985AN EFFICIENT TIMING MODEL FOR CMOS COMBINATIONAL LOGIC GATESWU, CY; HWANG, JS; CHANG, C; CHANG, CC; 電控工程研究所; Institute of Electrical and Control Engineering
1-Sep-1992NEW FAST FIXED-DELAY SIZING ALGORITHM FOR HIGH-PERFORMANCE CMOS COMBINATIONAL LOGIC-CIRCUITS AND ITS APPLICATIONSHWANG, JS; WU, CY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Jun-1989PHYSICAL TIMING MODELS OF SMALL-GEOMETRY CMOS INVERTERS AND MULTI-INPUT NAND NOR GATES AND THEIR APPLICATIONSWU, CY; HWANG, JS; 電子工程學系及電子研究所; 電控工程研究所; Department of Electronics Engineering and Institute of Electronics; Institute of Electrical and Control Engineering
1-May-1988TIMING MACROMODELS FOR CMOS STATIC SET RESET LATCHES AND THEIR APPLICATIONSWU, CY; LI, C; HWANG, JS; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics
Showing results 1 to 5 of 5