Browsing by Author Bhadra, Jayanta
Showing results 1 to 5 of 5
| Issue Date | Title | Author(s) |
| 2007 | An incremental learning framework for estimating signal controllability in unit-level verification | Wen, Charles H. -P.; Wang, Li-C.; Bhadra, Jayanta; 電信工程研究所; Institute of Communications Engineering |
| 2012 | An Intelligent Analysis of Iddq Data for Chip Classification in Very Deep-Submicron (VDSM) CMOS Technology | Chang, Chia-Ling (Lynn); Chang, Chia-Ching (Austin); Chan, Hui-Ling; Wen, Charles H. -P.; Bhadra, Jayanta; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2009 | Portable simulation/emulation stimulus on an industrial-strength SoC | Torres, Francisco; Srivastava, Rohit; Ruiz, Javier; Wen, H. -P.; Bose, Mrinal; Bhadra, Jayanta; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-一月-2013 | Process-Variation-Aware Iddq Diagnosis for Nano-Scale CMOS Designs - The First Step | Chang, Chia-Ling (Lynn); Wen, Charles H. -P; Bhadra, Jayanta; 電機工程學系; Department of Electrical and Computer Engineering |
| 2009 | Speeding up Bounded Sequential Equivalence Checking with Cross-Timeframe State-Pair Constraints from Data Learning | Chang, Chia-Ling(Lynn); Wen, Charles H. -P.; Bhadra, Jayanta; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
