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Issue DateTitleAuthor(s)
1-Jun-1993ANALYTICAL DESIGN FORMULATION FOR MINORITY-CARRIER WELL-TYPE GUARD RINGS IN CMOS CIRCUITSCHEN, MJ; HUANG, CY; TSENG, PN; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Feb-1995BASE CURRENT REVERSAL PHENOMENON IN A CMOS COMPATIBLE HIGH-GAIN N-P-N GATED LATERAL BIPOLAR-TRANSISTORHUANG, TH; CHEN, MJ; 電控工程研究所; Institute of Electrical and Control Engineering
1-Oct-1986CORRELATIONS BETWEEN CMOS LATCH-UP CHARACTERISTICS AND SUBSTRATE STRUCTURE PARAMETERSCHEN, MJ; WU, CY; 交大名義發表; 工學院; National Chiao Tung University; College of Engineering
1-Oct-1994DESIGN-MODEL AND GUIDELINE FOR N-WELL GUARD RING IN EPITAXIAL CMOSHUANG, CY; CHEN, MJ; 電子工程學系及電子研究所; 電控工程研究所; Department of Electronics Engineering and Institute of Electronics; Institute of Electrical and Control Engineering
1-May-1991EFFECT OF BACK-GATE BIAS ON TUNNELING LEAKAGE IN A GATED P+-N DIODECHEN, MJ; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering
1-May-1986AN EFFICIENT METHOD FOR CALCULATING THE DC TRIGGERING CURRENTS IN CMOS LATCH-UPCHEN, MJ; WU, CY; 交大名義發表; 工學院; National Chiao Tung University; College of Engineering
1-Apr-1986AN EFFICIENT TWO-DIMENSIONAL MODEL FOR CMOS LATCHUP ANALYSISCHEN, MJ; WU, CY; 交大名義發表; 工學院; National Chiao Tung University; College of Engineering
1-Jan-1995EMPIRICAL MODELING FOR GATE-CONTROLLED COLLECTOR CURRENT OF LATERAL BIPOLAR-TRANSISTORS IN AN N-MOSFET STRUCTUREHUANG, TH; CHEN, MJ; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Jan-1995FOWLER-NORDHEIM LIMITED BAND-TO-BAND TUNNELING (FNBB) FOR P-MOSFET GATE CURRENT IN A FLOATING BULK CONDITIONCHAO, KC; CHEN, MJ; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Dec-1992GATE AND DRAIN CURRENTS IN OFF-STATE BURIED-TYPE P-CHANNEL LDD MOSFETSCHEN, MJ; CHAO, KC; HUANG, TH; TSAUR, JM; 電控工程研究所; Institute of Electrical and Control Engineering
1-Apr-1986A NEW ANALYTICAL 3-DIMENSIONAL MODEL FOR SUBSTRATE RESISTANCE IN CMOS LATCHUP STRUCTURESCHEN, MJ; WU, CY; 交大名義發表; 工學院; National Chiao Tung University; College of Engineering
1985A NEW METHOD FOR COMPUTER-AIDED OPTIMIZATION OF SOLAR-CELL STRUCTURESCHEN, MJ; WU, CY; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering
1-May-1994NEW OBSERVATION AND THE MODELING OF GATE AND DRAIN CURRENTS IN OFF-STATE P-MOSFETSCHEN, MJ; CHAO, KC; CHEN, CH; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
3-Feb-1994NEW OBSERVATION OF CHARGE INJECTION IN MOS ANALOG SWITCHESCHEN, MJ; GU, YB; WU, T; HSU, PC; LIU, TH; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Sep-1991NEW OBSERVATION OF GATE CURRENT IN OFF-STATE MOSFETCHEN, MJ; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics
1-Apr-1987A NEW STRUCTURE-ORIENTED MODEL FOR WELL RESISTANCE IN CMOS LATCHUP STRUCTURESCHEN, MJ; SZE, SC; CHEN, HH; WU, CY; 交大名義發表; 工學院; National Chiao Tung University; College of Engineering
1-Feb-1992PREVENTIVE STRUCTURAL-ANALYSIS OF DATA-FLOW DIAGRAMSCHEN, MJ; CHUNG, CG; 交大名義發表; 資訊科學與工程研究所; National Chiao Tung University; Institute of Computer Science and Engineering
1-Jul-1991RESTRUCTURING OPERATIONS FOR DATA-FLOW DIAGRAMSCHEN, MJ; CHUNG, CG; 交大名義發表; 資訊科學與工程研究所; National Chiao Tung University; Institute of Computer Science and Engineering
1-Aug-1987A SIMPLIFIED COMPUTER-ANALYSIS FOR NORMAL-WELL GUARD RING EFFICIENCY IN CMOS CIRCUITSCHEN, MJ; WU, CY; 交大名義發表; 工學院; National Chiao Tung University; College of Engineering
1985A STRUCTURE-ORIENTED MODEL FOR DETERMINING THE SUBSTRATE SPREADING RESISTANCE IN BULK CMOS LATCH-UP PATHS AND ITS APPLICATION IN HOLDING CURRENT PREDICTIONCHEN, MJ; WU, CY; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering
Showing results 1 to 20 of 22  next >