瀏覽 的方式： 作者 Chen, Pai-Yu
顯示 1 到 2 筆資料，總共 2 筆
| 公開日期 | 標題 | 作者 |
| 13-十一月-2015 | Fully parallel write/read in resistive synaptic array for accelerating on-chip learning | Gao, Ligang; Wang, I-Ting; Chen, Pai-Yu; Vrudhula, Sarma; Seo, Jae-Sun; Cao, Yu; Hou, Tuo-Hung; Yu, Shimeng; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-一月-2015 | Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning | Chen, Pai-Yu; Lin, Binbin; Wang, I-Ting; Hou, Tuo-Hung; Ye, Jieping; Vrudhula, Sarma; Seo, Jae-sun; Cao, Yu; Yu, Shimeng; 交大名義發表; National Chiao Tung University |
