Browsing by Author Chen, Yi-Hang
Showing results 1 to 8 of 8
| Issue Date | Title | Author(s) |
| Jul-2016 | Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication Constraints | Chen, Yi-Hang; Chen, Jian-Yu; Huang, Juinn-Dar; 電機學院; 電子工程學系及電子研究所; College of Electrical and Computer Engineering; Department of Electronics Engineering and Institute of Electronics |
| 1-Jan-2014 | Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication Constraints | Chen, Yi-Hang; Chen, Jian-Yu; Huang, Juinn-Dar; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-Jan-2017 | Defect-Aware Synthesis for Reconfigurable Single-Electron Transistor Arrays | Huang, Juinn-Dar; Chen, Yi-Hang; Lu, Jia-Shin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2011 | Performance-Optimal Behavioral Synthesis with Degenerable Compound Functional Units | Huang, Juinn-Dar; Chen, Yi-Hang; Lin, Wan-Hsien; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2015 | ROBDD-Based Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays | Chen, Yi-Hang; Chen, Yang; Huang, Juinn-Dar; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2011 | Throughput Optimization for Latency-Insensitive System with Minimal Queue Insertion | Huang, Juinn-Dar; Chen, Yi-Hang; Ho, Ya-Chien; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-Jan-2014 | Two-Staged Parallel Layer-Aware Partitioning for 3D Designs | Chen, Yi-Hang; Chen, Yi-Ting; Huang, Juinn-Dar; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2016 | 應用於可重構式單電子電晶體陣列之合成技術 | 陳詣航; 黃俊達; Chen, Yi-Hang; Huang, Juinn-Dar; 電子研究所 |
