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Browsing by Author Chien, S. C.

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Showing results 1 to 8 of 8
Issue DateTitleAuthor(s)
2007The channel backscattering characteristics of sub-100nm CMOS devices with different channel/substrate orientationsTsai, Y. J.; Chung, Steve S.; Liu, P. W.; Tsai, C. H.; Lin, Y. H.; Tsai, C. T.; Ma, G. H.; Chien, S. C.; Sun, S. W.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2009Design of High-Performance and Highly Reliable nMOSFETs with Embedded Si:C S/D Extension Stressor(Si:C S/D-E)Chung, Steve S.; Hsieh, E. R.; Liu, P. W.; Chiang, W. T.; Tsai, S. H.; Tsai, T. L.; Huang, R. M.; Tsai, C. H.; Teng, W. Y.; Li, C. I.; Kuo, T. F.; Wang, Y. R.; Yang, C. L.; Tsai, C. T.; Ma, G. H.; Chien, S. C.; Sun, S. W.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2008More Strain and Less Stress- The Guideline for Developing High-End Strained CMOS Technologies with Acceptable ReliabilityChung, Steve S.; Hsieh, E. R.; Huang, D. C.; Lai, C. S.; Tsai, C. H.; Liu, P. W.; Lin, Y. H.; Tsai, C. T.; Ma, G. H.; Chien, S. C.; Sun, S. W.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2008New Observation of an Abnormal Leakage Current in Advanced CMOS Devices with Short Channel Lengths Down to 50nm and BeyondHsieh, E. R.; Chung, Steve S.; Lin, Y. H.; Tsai, C. H.; Liu, P. W.; Tsai, C. T.; Ma, G. H.; Chien, S. C.; Sun, S. W.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2006New observations on the uniaxial and biaxial strain-induced hot carrier and NBTI Reliabilities for 65nm node CMOS devices and beyondChung, Steve S.; Huang, D. C.; Tsai, Y. J.; Lai, C. S.; Tsai, C. H.; Liu, P. W.; Lin, Y. H.; Tsai, C. T.; Ma, G. H.; Chien, S. C.; Sun, S. W.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2008The Observation of Trapping and Detrapping Effects in High-k Gate Dielectric MOSFETs by a New Gate Current Random Telegraph Noise (I(G)-RTN) ApproachChang, C. M.; Chung, Steve S.; Hsieh, Y. S.; Cheng, L. W.; Tsai, C. T.; Ma, G. H.; Chien, S. C.; Sun, S. W.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2007Technology roadmaps on the ballistic transport in strain engineered nanoscale CMOS devicesChung, Steve S.; Tsai, Y. J.; Tsai, C. H.; Liu, P. W.; Lin, Y. H.; Tsai, C. T.; Ma, G. H.; Chien, S. C.; Sun, S. W.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2006Twin-GD: A new twin gated-diode measurement for the interface characterization of ultra-thin gate oxide MOSFET's with EOT down to 1nmLee, G. D.; Chung, S. S.; Mao, A. Y.; Lin, W. M.; Yang, C. W.; Hsieh, Y. S.; Chu, K. T.; Cheng, L. W.; Tai, H.; Hsu, L. T.; Lee, C. R.; Meng, H. L.; Tsai, C. T.; Ma, G. H.; Chien, S. C.; Sun, S. W.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
Showing results 1 to 8 of 8