| Issue Date | Title | Author(s) |
| 1-Jan-2017 | An Analytical Placer for Heterogeneous FPGAs via Rough-Placed Packing | Wu, Wan-Ning; Chen, Chen; Chin, Ching-Yu; Wang, Chun-Kai; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-Nov-2014 | Clock Tree Synthesis Considering Slew Effect on Supply Voltage Variation | Wang, Chun-Kai; Chang, Yeh-Chi; Chen, Hung-Ming; Chin, Ching-Yu; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2013 | Efficient Analog Layout Prototyping by Layout Reuse with Routing Preservation | Chin, Ching-Yu; Pan, Po-Cheng; Chen, Hung-Ming; Chen, Tung-Chieh; Lin, Jou-Chun; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-Mar-2013 | Escaped Boundary Pins Routing for High-Speed Boards | Chin, Ching-Yu; Kuan, Chung-Yi; Tsai, Tsung-Ying; Chen, Hung-Ming; Kajitani, Yoji; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-Sep-2015 | A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation | Pan, Po-Cheng; Chin, Ching-Yu; Chen, Hung-Ming; Chen, Tung-Chieh; Lee, Chin-Chieh; Lin, Jou-Chun; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-Jun-2014 | Fast Thermal Aware Placement With Accurate Thermal Analysis Based on Green Function | Liu, Sean Shih-Ying; Luo, Ren-Guo; Aroonsantidecha, Suradeth; Chin, Ching-Yu; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2012 | A Fast Thermal Aware Placement with Accurate Thermal Analysis Based on Green Function | Aroonsantidecha, Suradeth; Liu, Sean Shih-Ying; Chin, Ching-Yu; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2009 | Fault Models for Embedded-DRAM Macros | Chao, Mango C. -T.; Yang, Hao-Yu; Huang, Rei-Fu; Lin, Shih-Chin; Chin, Ching-Yu; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2010 | Mathematical Yield Estimation for Two-Dimensional-Redundancy Memory Arrays | Chao, Mango C. -T.; Chin, Ching-Yu; Lin, Chen-Wei; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-Jan-2013 | Mean-time-to-crack Model of Microbump Interconnect in FCGBA Package under Thermal Cyclic Test | Chen, Chien-Chang; Wu, Wei-Chen; Chin, Ching-Yu; Chen, Hung-Ming; Lin, Vito; Chen, Eason; 丘成桐中心; 電子工程學系及電子研究所; Shing-Tung Yau Center; Department of Electronics Engineering and Institute of Electronics |
| 1-Dec-2011 | A Novel Test Flow for One-Time-Programming Applications of NROM Technology | Chao, Mango C. -T.; Chin, Ching-Yu; Tsou, Yao-Te; Chang, Chi-Min; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2009 | A Novel Test Flow for One-Time-Programming Applications of NROM Technology | Chin, Ching-Yu; Tsou, Yao-Te; Chang, Chi-Min; Chao, Mango C. -T.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-Jan-2011 | On Routing Fixed Escaped Boundary Pins for High Speed Boards | Tsai, Tsung-Ying; Lee, Ren-Jie; Chin, Ching-Yu; Kuan, Chung-Yi; Chen, Hung-Ming; Kajitani, Yoji; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-Jan-2013 | On Simultaneous Escape Routing of Length Matching Differential Signalings | Lee, Yen-Jung; Chen, Hung-Ming; Chin, Ching-Yu; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-Jan-2013 | Simultaneous Escape Routing on Multiple Components for Dense PCBs | Chin, Ching-Yu; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2017 | 客製化繞線模型與演算法 | 秦敬雨; 陳宏明; Chin, Ching-Yu; Chen, Hung-Ming; 電子研究所 |
