National Chiao Tung University Institutional Repository：瀏覽交通大學機構典藏

瀏覽的方式：作者 Chiu, Po-Yen

顯示 1 到 11 筆資料，總共 11 筆

公開日期	標題	作者
1-十月-2013	Design of 2 x V-DD-Tolerant I/O Buffer With PVT Compensation Realized by Only 1 x V-DD Thin-Oxide Devices	Ker, Ming-Dou; Chiu, Po-Yen; 電子工程學系及電子研究所; 生醫電子轉譯研究中心; Department of Electronics Engineering and Institute of Electronics; Biomedical Electronics Translational Research Center
1-一月-2013	DESIGN OF 2xV(DD) LOGIC GATES WITH ONLY 1xV(DD) DEVICES IN NANOSCALE CMOS TECHNOLOGY	Chiu, Po-Yen; Ker, Ming-Dou; 電機學院; College of Electrical and Computer Engineering
2007	ESD protection design for giga-Hz high-speed I/O interfaces in a 130-nm CMOS process	Hsiao, Yuan-Wen; Ker, Ming-Dou; Chiu, Po-Yen; Huang, Chun; Tseng, Yuh-Kuang; 電機學院; College of Electrical and Computer Engineering
二月-2017	ESD Protection Design for Touch Panel Control IC Against Latchup-Like Failure Induced by System-Level ESD Test	Ker, Ming-Dou; Chiu, Po-Yen; Shieh, Wuu-Trong; Wang, Chun-Chi; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Jan-2017	ESD-Induced Latchup-Like Failure in a Touch Panel Control IC	Ker, Ming-Dou; Chiu, Po-Yen; Shieh, Wuu-Trong; Wang, Chun-Chi; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2012	Failure Analysis on Gate-Driven ESD Clamp Circuit after TLP Stresses of Different Voltage Steps in a 16-V CMOS Process	Dai, Chia-Tsen; Chiu, Po-Yen; Ker, Ming-Dou; Tsai, Fu-Yi; Peng, Yan-Hua; Tsai, Chia-Ku; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Jan-2014	Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuit	Chiu, Po-Yen; Ker, Ming-Dou; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Sep-2011	New Low-Leakage Power-Rail ESD Clamp Circuit in a 65-nm Low-Voltage CMOS Process	Ker, Ming-Dou; Chiu, Po-Yen; 電機學院; College of Electrical and Computer Engineering
2009	On the Design of Power-Rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-Voltage CMOS Process	Ker, Ming-Dou; Chiu, Po-Yen; Tsai, Fu-Yi; Chang, Yeong-Jar; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2009	Ultra-Low-Leakage Power-Rail ESD Clamp Circuit in Nanoscale Low-Voltage CMOS Process	Chiu, Po-Yen; Ker, Ming-Dou; Tsai, Fu-Yi; Chang, Yeong-Jar; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2013	系統單晶片應用之靜電放電箝制電路與輸出緩衝器可靠度設計	邱柏硯; Chiu, Po-Yen; 柯明道; Ker, Ming-Dou; 電子工程學系電子研究所

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