Browsing by Author Chou, Hung-Mu
Showing results 1 to 5 of 5
| Issue Date | Title | Author(s) |
| 2005 | A compact model for electrostatic discharge protection nanoelectronics simulation | Chou, Hung-Mu; Yu, Shao-Ming; Lee, Jam-Wem; Li, Yiming; 電信工程研究所; 友訊交大聯合研發中心; Institute of Communications Engineering; D Link NCTU Joint Res Ctr |
| 1-Feb-2007 | A floating gate design for electrostatic discharge protection circuits | Chou, Hung-Mu; Lee, Jam-Wen; Li, Yiming; 電信工程研究所; 友訊交大聯合研發中心; Institute of Communications Engineering; D Link NCTU Joint Res Ctr |
| 2005 | Hybrid evolutionary approach to optimal design of CMOS LNA integrated circuits | Li, Yiming; Chou, Hung-Mu; 電信工程研究所; Institute of Communications Engineering |
| 2005 | Parallel simulation of deep sub-micron double-gate metal-oxide-semiconductor field effect transistors | Yu, Shao-Ming; Chou, Hung-Mu; Lo, Shih-Ching; 資訊工程學系; Department of Computer Science |
| 1-Oct-2004 | Silicon-Germanium Structure in Surrounding-Gate Strained Silicon Nanowire Field Effect Transistors | Li, Yiming; Lee, Jam-Wem; Chou, Hung-Mu; 電子物理學系; 友訊交大聯合研發中心; Department of Electrophysics; D Link NCTU Joint Res Ctr |
