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Browsing by Author Chou, K. I.

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Showing results 1 to 5 of 5
Issue DateTitleAuthor(s)
1-Apr-2013Achieving low sub-0.6-nm EOT in gate-first n-MOSFET with TiLaO/CeO2 gate stackCheng, C. H.; Chou, K. I.; Chin, Albert; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Sep-2013Gate-first n-MOSFET with a sub-0.6-nm EOT gate stackCheng, C. H.; Chou, K. I.; Chin, A.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Jan-2014Low power resistive random access memory using interface-engineered dielectric stack of SiOx/a-Si/TiOy with 1D1R-like structureCheng, Chun-Hu; Chou, K. I.; Zheng, Zhi-Wei; Hsu, Hsiao-Hsuan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Feb-2015Low-Voltage InGaZnO Thin Film Transistors with Small Sub-Threshold SwingCheng, C. H.; Chou, K. I.; Hsu, H. H.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Apr-2013Ni/GeOx/TiOy/TaN RRAM on Flexible Substrate With Excellent Resistance DistributionChou, K. I.; Cheng, C. H.; Zheng, Z. W.; Liu, Ming; Chin, Albert; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
Showing results 1 to 5 of 5