瀏覽 的方式： 作者 Chou, Teyuh
顯示 1 到 5 筆資料，總共 5 筆
| 公開日期 | 標題 | 作者 |
| 9-九月-2016 | 3D Ta/TaOx/TiO2/Ti synaptic array and linearity tuning of weight update for hardware neural network applications | Wang, I-Ting; Chang, Chih-Cheng; Chiu, Li-Wen; Chou, Teyuh; Hou, Tuo-Hung; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-一月-2017 | Challenges and Opportunities toward Online Training Acceleration using RRAM-based Hardware Neural Network | Chang, Chih-Cheng; Liu, Jen-Chieh; Shen, Yu-Lin; Chou, Teyuh; Chen, Pin-Chun; Wang, I-Ting; Su, Chih-Chun; Wu, Ming-Hong; Hudec, Boris; Chang, Che-Chia; Tsai, Chia-Ming; Chang, Tian-Sheuan; Wong, H-S Philip; Hou, Tuo-Hung; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-一月-2016 | Development of Three-Dimensional Synaptic Device and Neuromorphic Computing Hardware | Wang, I-Ting; Chou, Teyuh; Chiu, Li-Wen; Chang, Chih-Cheng; Hou, Tuo-Hung; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-三月-2018 | Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network Based on Analog Resistive Synapse | Chang, Chih-Cheng; Chen, Pin-Chun; Chou, Teyuh; Wang, I-Ting; Hudec, Boris; Chang, Che-Chia; Tsai, Chia-Ming; Chang, Tian-Sheuan; Hou, Tuo-Hung; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2016 | 應用類比電阻仿生神經突觸之硬體神經網路系統實現 | 周德玉; 侯拓宏; Chou, Teyuh; Hou, Tuo-Hung; 電子研究所 |
