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Showing results 1 to 5 of 5
Issue DateTitleAuthor(s)
1-Feb-1994ANALYSIS OF BILATERAL LATCH-UP TRIGGERING IN VLSI CIRCUITSHUANG, HS; CHANG, CY; HSU, CC; CHEN, KL; LIN, JK; 電控工程研究所; Institute of Electrical and Control Engineering
1-Nov-1993THE BEHAVIOR OF BILATERAL LATCH-UP TRIGGERING IN VLSI ELECTROSTATIC DISCHARGE DAMAGE PROTECTION CIRCUITSHUANG, HS; CHANG, CY; HSU, CC; CHEN, KL; LIN, JK; 電控工程研究所; Institute of Electrical and Control Engineering
1-Apr-1991COMPLEX-SURFACE MODELING WITH BIAS AND TENSIONCHEN, DP; LIN, TL; HSU, CC; 交大名義發表; 機械工程學系; National Chiao Tung University; Department of Mechanical Engineering
1-Nov-1993DISTRIBUTED TASK ASSIGNMENT USING CRITICAL PATH ESTIMATEHSU, CC; LEE, PJ; 資訊科學與工程研究所; Institute of Computer Science and Engineering
1-Jan-1994A STUDY ON BILATERAL LATCH-UP SELF-TRIGGERING IN COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR PROTECTION CIRCUITSHUANG, HS; CHANG, CY; CHEN, KL; LIU, IO; HSU, CC; LIN, JK; 電控工程研究所; Institute of Electrical and Control Engineering
Showing results 1 to 5 of 5