瀏覽 的方式： 作者 HWANG, JS
顯示 1 到 5 筆資料，總共 5 筆
| 公開日期 | 標題 | 作者 |
| 1-五月-1991 | EFFICIENT TECHNIQUES IN THE SIZING AND CONSTRAINED OPTIMIZATION OF CMOS COMBINATIONAL LOGIC-CIRCUITS | HWANG, JS; WU, CY; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics |
| 1985 | AN EFFICIENT TIMING MODEL FOR CMOS COMBINATIONAL LOGIC GATES | WU, CY; HWANG, JS; CHANG, C; CHANG, CC; 電控工程研究所; Institute of Electrical and Control Engineering |
| 1-九月-1992 | NEW FAST FIXED-DELAY SIZING ALGORITHM FOR HIGH-PERFORMANCE CMOS COMBINATIONAL LOGIC-CIRCUITS AND ITS APPLICATIONS | HWANG, JS; WU, CY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-六月-1989 | PHYSICAL TIMING MODELS OF SMALL-GEOMETRY CMOS INVERTERS AND MULTI-INPUT NAND NOR GATES AND THEIR APPLICATIONS | WU, CY; HWANG, JS; 電子工程學系及電子研究所; 電控工程研究所; Department of Electronics Engineering and Institute of Electronics; Institute of Electrical and Control Engineering |
| 1-五月-1988 | TIMING MACROMODELS FOR CMOS STATIC SET RESET LATCHES AND THEIR APPLICATIONS | WU, CY; LI, C; HWANG, JS; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics |
