瀏覽 的方式： 作者 Hou, CS
顯示 1 到 7 筆資料，總共 7 筆
| 公開日期 | 標題 | 作者 |
| 1-四月-1998 | Back-gate bias enhanced band-to-band tunneling leakage in scaled MOSFET's | Chen, MJ; Huang, HT; Hou, CS; Yang, KN; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-三月-1996 | A design strategy for short gate length SOI MESFETs | Hou, CS; Wu, CY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-四月-2002 | Impact of a large earthquake on a GPS network: The case of the 1999 Chi-Chi, Taiwan earthquake | Kuo, LC; Yu, SB; Hsu, VJ; Hou, CS; Lee, YH; Tsai, CS; Chen, CS; 土木工程學系; Department of Civil Engineering |
| 1-四月-2000 | Monte Carlo sphere model for effective oxide thinning induced extrinsic breakdown | Huang, HT; Chen, MJ; Chen, JH; Su, CW; Hou, CS; Liang, MS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-七月-1999 | A novel cross-coupled inter-poly-oxide capacitor for mixed-mode CMOS processes | Chen, MJ; Hou, CS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-八月-1998 | A physical model for the correlation between holding voltage and holding current in epitaxial CMOS latch-up | Chen, MJ; Lee, HS; Chen, JH; Hou, CS; Lin, CS; Jou, YN; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-六月-2001 | A trap generation closed-form statistical model for intrinsic oxide breakdown | Huang, HT; Chen, MJ; Su, CW; Chen, JH; Hou, CS; Liang, MS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
