Browsing by Author Huang, JD
Showing results 1 to 11 of 11
| Issue Date | Title | Author(s) |
| 1-Aug-2000 | ALTO: An iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping | Huang, JD; Jou, JY; Shen, WZ; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1996 | BDD based lambda set selection in Roth-Karp decomposition for LUT architecture | Jiang, JH; Jou, JY; Huang, JD; Wei, JS; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics |
| 1998 | Compatible class encoding in hyper-function decomposition for FPGA synthesis | Jiang, JHR; Jou, JY; Huang, JD; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1995 | Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture | Huang, JD; Joy, JY; Shen, WZ; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2005 | Formal compliance verification of interface protocols | Yang, YC; Huang, JD; Yen, CC; Shih, CH; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1996 | An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping | Huang, JD; Jou, JY; Shen, WZ; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics |
| 1-Dec-1998 | On circuit clustering for area/delay tradeoff under capacity and pin constraints | Huang, JD; Jou, JY; Shen, WZ; Chuang, HH; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2005 | Stimulus generation for interface protocol verification using the non-deterministic extended finite state machine model | Shih, CH; Huang, JD; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-Apr-2001 | Unified functional decomposition via encoding for FPGA technology mapping | Jiang, JH; Jou, JY; Huang, JD; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-Oct-1997 | A variable partitioning algorithm of BDD for FPGA technology mapping | Jiang, JH; Jou, JY; Huang, JD; Wei, JS; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics |
| 2004 | Verification on port connections | Lee, GW; Wang, CY; Huang, JD; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
