Skip navigation
Browse
Items
Issue Date
Author
Title
Subject
Researchers
English
繁體
简体
You are Here:
National Chiao Tung University Institutional Repository
Browsing by Author Jiang, HC
Jump to:
0-9
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
or enter first few letters:
Sort by:
title
issue date
submit date
In order:
Ascending
Descending
Results/Page
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
Authors/Record:
All
1
5
10
15
20
25
30
35
40
45
50
Showing results 1 to 14 of 14
Issue Date
Title
Author(s)
1-Feb-1999
A 2-D velocity- and direction-selective sensor with BJT-based silicon retina and temporal zero-crossing detector
Jiang, HC
;
Wu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
1-Jan-2003
Active device under bond pad to save I/O layout for high-pin-count SOC
Ker, MD
;
Peng, JJ
;
Jiang, HC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
2001
Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's
Ker, MD
;
Jiang, HC
;
Peng, JJ
;
Shieh, TL
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
1998
The BJT-based silicon-retina sensory system for direction- and velocity-selective sensing
Jiang, HC
;
Wu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
2000
Design of low-capacitance bond pad for high-frequency I/O applications in CMOS integrated circuits
Ker, MD
;
Jiang, HC
;
Chang, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
2002
Design of negative charge pump circuit with polysilicon diodes in a 0.25-mu m CMOS process
Ker, MD
;
Chang, CY
;
Jiang, HC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
1-Dec-2001
Design on the low-capacitance bond pad for high-frequency I/O circuits in CMOS technology
Ker, MD
;
Jiang, HC
;
Chang, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
2001
ESD test methods on integrated circuits: An overview
Ker, MD
;
Peng, JH
;
Jiang, HC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
2002
Failure analysis of ESD damage in a high-voltage driver IC and the effective ESD protection solution
Ker, MD
;
Peng, JJ
;
Jiang, HC
;
電機學院
;
College of Electrical and Computer Engineering
1-Jun-1999
An improved BJT-based silicon retina with tunable image smoothing capability
Wu, CY
;
Jiang, HC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
1-May-2001
In the blink of a silicon eye
Cheng, CH
;
Wu, CY
;
Sheu, B
;
Lin, LJ
;
Huang, KH
;
Jiang, HC
;
Yen, WC
;
Hsiao, CW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
2002
Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits
Peng, JJ
;
Ker, MD
;
Jiang, HC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
2003
Test structure and verification on the MOSFET under bond pad for area-efficient I/O layout in high-pin-count SOCIC's
Ker, MD
;
Peng, JJ
;
Jiang, HC
;
電機學院
;
College of Electrical and Computer Engineering
2001
Whole-chip ESD protection strategy for CMOS integrated circuits in nanotechnology
Ker, MD
;
Jiang, HC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics