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Showing results 1 to 5 of 5
Issue DateTitleAuthor(s)
1-Sep-2000Crosstalk-driven interconnect optimization by simultaneous gate and wire sizingJiang, IHR; Chang, YW; Jou, JY; 資訊工程學系; 電子工程學系及電子研究所; Department of Computer Science; Department of Electronics Engineering and Institute of Electronics
1-Nov-1999Internet-based hierarchical floorplan designLin, JH; Jou, JY; Jiang, IHR; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2001On placement and routing of wafer scale memorySung, LA; Jiang, IHR; Chang, YW; Jou, JY; Wu, JC; Feng, TS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Jan-2006Reliable crosstalk-driven interconnect optimizationJiang, IHR; Pan, SR; Chang, YW; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-May-2004Simultaneous floorplan and buffer-block optimizationJiang, IHR; Chang, YW; Jou, JY; Chao, KY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
Showing results 1 to 5 of 5