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Showing results 1 to 5 of 5
Issue DateTitleAuthor(s)
1-Nov-2009The Dependence of the Performance of Strained NMOSFETs on Channel WidthYeh, Lingyen; Liao, Ming Han; Chen, Chun Heng; Wu, Jun; Lee, Joseph Ya-Min; Liu, Chee Wee; Lee, T. L.; Liang, M. S.; 材料科學與工程學系; Department of Materials Science and Engineering
1-Feb-2007Effect of gate sinking on the device performance, of the InGaP/AlGaAs/InGaAs enhancement-mode PHEMTChu, L. H.; Chang, E. Y.; Chang, L.; Wu, Y. H.; Chen, S. H.; Hsu, H. T.; Lee, T. L.; Lien, Y. C.; Chang, C. Y.; 材料科學與工程學系; 電子工程學系及電子研究所; Department of Materials Science and Engineering; Department of Electronics Engineering and Institute of Electronics
12-Dec-2012A novel technique to fabricate 28 nm p-MOSFETs possessing gate oxide integrity on an embedded SiGe channel without silicon surface passivationYu, M. H.; Liao, M. H.; Huang, T. C.; Wang, L. T.; Lee, T. L.; Jang, S. M.; Cheng, H. C.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2006Relaxation-free strained SiGe with super anneal for 32nm high performance PMOS and beyondYu, Ming H.; Li, J. H.; Lin, H. H.; Chen, C. H.; Ku, K. C.; Nieh, C. F.; Hisa, H.; Sheu, Y. M.; Tsai, C. W.; Wang, Y. L.; Chu, H. Y.; Cheng, H. C.; Lee, T. L.; Chen, S. C.; Liang, M. S.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2012The Strained-SiGe Relaxation Induced Underlying Si Defects Following the Millisecond Annealing for the 32 nm PMOSFETsYu, M. H.; Wang, L. T.; Huang, T. C.; Lee, T. L.; Cheng, H. C.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
Showing results 1 to 5 of 5