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Browsing by Author Lee, TGY

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Issue DateTitleAuthor(s)
1-May-2000An empirical three-dimensional crossover capacitance model for multilevel interconnect VLSI circuitsWong, SC; Lee, TGY; Ma, DJ; Chao, CJ; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Dec-2001Generalized interconnect delay time and crosstalk models: I. Applications of interconnect optimization designLee, TGY; Tseng, TY; Wong, SC; Yang, CJ; Liang, MS; Cheng, HC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Dec-2001Generalized interconnect delay time and crosstalk models: II. Crosstalk-induced delay time deterioration and worst crosstalk modelsLee, TGY; Tseng, TY; Wong, SC; Yang, CJ; Liang, MS; Cheng, HC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
Showing results 1 to 3 of 3