National Chiao Tung University Institutional Repository：Browsing IR@NCTU

Browsing by Author Lin, Geeng-Lih

Showing results 1 to 7 of 7

Issue Date	Title	Author(s)
2015	ESD Protection Design with Latchup-Free Immunity in 120V SOI Process	Huang, Yi-Jie; Ker, Ming-Dou; Huang, Yeh-Jen; Tsai, Chun-Chien; Jou, Yeh-Ning; Lin, Geeng-Lih; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2006	Experimental evaluation and device simulation of device structure influences on latchup immunity in high-voltage 40-V CMOS process	Hsu, Sheng-Fu; Ker, Ming-Dou; Lin, Geeng-Lih; Jou, Yeh-Ning; 電機學院; College of Electrical and Computer Engineering
2015	Impact of Guard Ring Layout on the Stacked Low-Voltage PMOS for High-Voltage ESD Protection	Liao, Seian-Feng; Tang, Kai-Neng; Ker, Ming-Dou; Yeh, Jia-Rong; Chiou, Hwa-Chyi; Huang, Yeh-Jen; Tsai, Chun-Chien; Jou, Yeh-Ning; Lin, Geeng-Lih; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2007	The impact of high-voltage drift n-well and shallow trench isolation layouts on electrical characteristics of LDMOSFETs	Huang, C. T.; Tsui, Bing-Yue; Liu, Hsu-Ju; Lin, Geeng-Lih; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2009	Improvement on ESD Robustness of Lateral DMOS in High-Voltage CMOS ICs by Body Current Injection	Chen, Wen-Yi; Ker, Ming-Dou; Jou, Yeh-Ning; Huang, Yeh-Jen; Lin, Geeng-Lih; 電機學院; College of Electrical and Computer Engineering
2008	Measurement on Snapback Holding Voltage of High-Voltage LDMOS for Latch-up Consideration	Chen, Wen-Yi; Ker, Ming-Dou; Huang, Yeh-Jen; Jou, Yeh-Ning; Lin, Geeng-Lih; 電機學院; College of Electrical and Computer Engineering
2015	Stacked Low-Voltage PMOS for High-Voltage ESD Protection with Latchup-Free Immunity	Tang, Kai-Neng; Liao, Seian-Feng; Ker, Ming-Dou; Chiou, Hwa-Chyi; Huang, Yeh-Jen; Tsai, Chun-Chien; Jou, Yeh-Ning; Lin, Geeng-Lih; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics

Showing results 1 to 7 of 7