瀏覽 的方式： 作者 Lu, Chao-Hung
顯示 1 到 7 筆資料，總共 7 筆
| 公開日期 | 標題 | 作者 |
| 1-一月-2011 | Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits | Lu, Chao-Hung; Chen, Hung-Ming; Liu, Chien-Nan Jimmy; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-九月-2008 | Effective Decap Insertion in Area-Array SoC Floorplan Design | Lu, Chao-Hung; Chen, Hung-Ming; Liu, Chien-Nan Jimmy; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-一月-2008 | An effective decap insertion method considering power supply noise during floorplanning | Lu, Chao-Hung; Chen, Hung-Ming; Liu, Chien-Nan Jimmy; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2007 | On increasing signal integrity with minimal decap insertion in area-array SoC floorplan design | Lu, Chao-Hung; Chen, Hung-Ming; Liu, Chien-Nan Jimmy; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2009 | Package Routability- and IR-Drop-Aware Finger/Pad Assignment in Chip-Package Co-Design | Lu, Chao-Hung; Chen, Hung-Ming; Liu, Chien-Nan Jimmy; Shih, Wen-Yu; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-Jun-2013 | Package routability- and IR-drop-aware finger/pad planning for single chip and stacking IC designs | Lu, Chao-Hung; Chen, Hung-Ming; Liu, Chien-Nan Jimmy; Shih, Wen-Yu; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-Jan-2007 | Using power gating techniques in area-array SoC floorplan design | Yeh, Chi-Yi; Chen, Hung-Ming; Huang, Li-Da; Wei, Wei-Ting; Lu, Chao-Hung; Liu, Chien-Nan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
