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Showing results 1 to 9 of 9
Issue DateTitleAuthor(s)
1-Jan-2003Active device under bond pad to save I/O layout for high-pin-count SOCKer, MD; Peng, JJ; Jiang, HC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2001Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC'sKer, MD; Jiang, HC; Peng, JJ; Shieh, TL; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2003Electrostatic discharge implantation to improve machine-model ESD robustness of stacked NMOS in mixed-voltage I/O interface circuitsKer, MD; Hsu, HC; Peng, JJ; 電機學院; College of Electrical and Computer Engineering
1-Oct-2003ESD implantation for subquarter-micron CMOS technology to enhance ESD robustnessKer, MD; Hsu, HC; Peng, JJ; 電機學院; College of Electrical and Computer Engineering
2002Failure analysis of ESD damage in a high-voltage driver IC and the effective ESD protection solutionKer, MD; Peng, JJ; Jiang, HC; 電機學院; College of Electrical and Computer Engineering
1-Jun-2002Fully process-compatible layout design on bond pad to improve wire bond reliability in CMOS ICsKer, MD; Peng, JJ; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2002Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuitsPeng, JJ; Ker, MD; Jiang, HC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
15-Nov-2002Novel implantation method to improve machine-model electrostatic discharge robustness of stacked N-channel metal-oxide semiconductors (NMOS) in sub-quarter-micron complementary metal-oxide semiconductors (CMOS) technologyKer, MD; Hsu, HC; Peng, JJ; 電機學院; College of Electrical and Computer Engineering
2003Test structure and verification on the MOSFET under bond pad for area-efficient I/O layout in high-pin-count SOCIC'sKer, MD; Peng, JJ; Jiang, HC; 電機學院; College of Electrical and Computer Engineering
Showing results 1 to 9 of 9