| 公開日期 | 標題 | 作者 |
| 1981 | AN ANALYTICAL MODEL FOR HIGH-LOW-EMITTER (HLE) SOLAR-CELLS IN CONCENTRATED SUNLIGHT | SHEN, WZ; WU, CY; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering |
| 1994 | A CELL-BASED POWER ESTIMATION IN CMOS COMBINATIONAL CIRCUITS | LIN, JY; LIU, TC; SHEN, WZ; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 7-十二月-1989 | CIRCUIT EXAMPLE TO DEMONSTRATE THAT FAN-OUT STEMS OF PRIMARY INPUTS MUST BE CHECKPOINTS | CHEN, JE; LEE, CL; SHEN, WZ; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering |
| 1-Jul-1993 | DESIGN OF PSEUDOEXHAUSTIVE TESTABLE PLA WITH LOW OVERHEAD | SHEN, WZ; HWANG, GH; HSU, WJ; JAN, YJ; 電控工程研究所; Institute of Electrical and Control Engineering |
| 1-Oct-1993 | EFFICIENT OUTPUT PHASE ASSIGNMENT ALGORITHM FOR PLAS | HSU, WJ; SHEN, WZ; 電控工程研究所; Institute of Electrical and Control Engineering |
| 1-Aug-1990 | EMOTA - AN EVENT-DRIVEN MOS TIMING SIMULATOR FOR VLSI CIRCUITS | SHEN, WZ; JOU, SJ; TAO, YS; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics |
| 1-Feb-1993 | EVENT-DRIVEN INCREMENTAL TIMING FAULT SIMULATOR | JOU, SJ; CHIOU, SH; TAO, YS; SHEN, WZ; 電控工程研究所; Institute of Electrical and Control Engineering |
| 1995 | Lambda set selection in Roth-Karp decomposition for LUT-based FPGA technology mapping | SHEN, WZ; HUANG, JD; CHAO, SM; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-Oct-1986 | MOTA - A MOSFET TIMING SIMULATOR | JOU, SJ; JEN, CW; SHEN, WZ; LEE, CL; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering |
| 1-Jun-1990 | MY-BOX REPRESENTATION FOR FAULTY CMOS CIRCUITS | CHEN, JE; LEE, CL; SHEN, WZ; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering |
| 1994 | ON THE REDUCTION OF REORDER BUFFER SIZE FOR DISCRETE FOURIER TRANSFORM PROCESSOR DESIGN | SHEN, WZ; TAO, YH; DUNG, LR; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1980 | THE OPEN-CIRCUIT VOLTAGE OF BACK-SURFACE-FIELD (BSF) P-N-JUNCTION SOLAR-CELLS IN CONCENTRATED SUNLIGHT | WU, CY; SHEN, WZ; 電控工程研究所; 奈米中心; Institute of Electrical and Control Engineering; Nano Facility Center |
| 1-Apr-1993 | RESTRUCTURING AND LOGIC MINIMIZATION FOR TESTABLE PLA | HWANG, GH; SHEN, WZ; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-Apr-1993 | SEESIM - A FAST SYNCHRONOUS SEQUENTIAL-CIRCUIT FAULT SIMULATOR WITH SINGLE-EVENT EQUIVALENCE | WU, CP; LEE, CL; SHEN, WZ; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-Dec-1987 | SIMULATABLE TIMING MODEL FOR MOS LOGIC-CIRCUIT | JOU, SJ; SHEN, WZ; JEN, CW; LEE, CL; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering |
| 1-Dec-1991 | SINGLE-FAULT FAULT-COLLAPSING ANALYSIS IN SEQUENTIAL LOGIC-CIRCUITS | CHEN, JE; LEE, CL; SHEN, WZ; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
