Browsing by Author SHUNG, CB
Showing results 1 to 9 of 9
| Issue Date | Title | Author(s) |
| 1-Dec-1991 | A 30-MHZ TRELLIS CODEC CHIP FOR PARTIAL-RESPONSE CHANNELS | SHUNG, CB; SIEGEL, PH; THAPAR, HK; KARABED, R; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-Apr-1993 | AREA-EFFICIENT ARCHITECTURES FOR THE VITERBI ALGORITHM .1. THEORY | SHUNG, CB; LIN, HD; CYPHER, R; SIEGEL, PH; THAPAR, HK; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-May-1993 | AREA-EFFICIENT ARCHITECTURES FOR THE VITERBI ALGORITHM .2. APPLICATIONS | SHUNG, CB; LIN, HD; CYPHER, R; SIEGEL, PH; THAPAR, HK; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1994 | FAULT-TOLERANT ARCHITECTURES FOR SHARED BUFFER MEMORY SWITCH | LIN, YF; SHUNG, CB; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-Jan-1993 | GENERALIZED TRACE-BACK TECHNIQUES FOR SURVIVOR MEMORY MANAGEMENT IN THE VITERBI ALGORITHM | CYPHER, R; SHUNG, CB; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1994 | A HIGH SPEED REED-SOLOMON CODEC CHIP USING LOOKFORWARD ARCHITECTURE | CHANG, JY; SHUNG, CB; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-Apr-1991 | AN INTEGRATED CAD SYSTEM FOR ALGORITHM-SPECIFIC IC DESIGN | SHUNG, CB; JAIN, R; RIMEY, K; WANG, E; SRIVASTAVA, MB; RICHARDS, BC; LETTANG, E; AZIM, SK; THON, L; HILFINGER, PN; RABAEY, JM; BRODERSEN, RW; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-Nov-1993 | REAL-TIME RECORDING RESULTS FOR A TRELLIS-CODED PARTIAL-RESPONSE (TCPR) SYSTEM | THAPAR, HK; SHUNG, CB; RAE, JW; KARABED, R; SIEGEL, PH; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-Jul-1995 | SHARED BUFFER ATM SWITCH WITH DOUBLY LINKED LISTS | LIN, YF; SHUNG, CB; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
