| 公開日期 | 標題 | 作者 |
| 2007 | Accurate modeling and characterization of mobility in tensile and compressive stress for state-of-the-art manufacturing NMOSFETs | Wang, J. -S.; Chen, William P. N.; Shih, C. -H.; Lien, C.; Su, Pin; Sheu, Y. M.; Chao, Donald Y. -S.; Goto, K.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-六月-2015 | Analysis of GeOI FinFET 6T SRAM Cells With Variation-Tolerant WLUD Read-Assist and TVC Write-Assist | Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2013 | Analysis of Germanium FinFET Logic Circuits and SRAMs with Asymmetric Gate to Source/Drain Underlap Devices | Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-六月-2013 | Analysis of Single-Trap-Induced Random Telegraph Noise and its Interaction With Work Function Variation for Tunnel FET | Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nein; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-八月-2012 | Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits | Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-八月-2012 | "Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits" | Fan, Ming-Long; Hu, Vita Pi-Ho; Chen, Yin-Nien; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-九月-2011 | Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity | Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-九月-2011 | Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity | Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-十一月-2009 | Analytical Quantum-Confinement Model for Short-Channel Gate-All-Around MOSFETs Under Subthreshold Region | Wu, Yu-Sheng; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2014 | Anomalous Electrostatics and Intrinsic Variability in GeOI p-MOSFET | Yu, Chang-Hung; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-二月-2012 | Band-to-Band-Tunneling Leakage Suppression for Ultra-Thin-Body GeOI MOSFETs Using Transistor Stacking | Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-一月-2016 | Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM Cells | Yu, Chang-Hung; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-八月-2014 | Built-in Effective Body-Bias Effect in Ultra-Thin-Body Hetero-Channel III-V-on-Insulator n-MOSFETs | Yu, Chang-Hung; Su, Pin; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics |
| 2015 | Built-in Effective Body-Bias Effect in UTBB Hetero-Channel MOSFETs and Its Suppression | Yu, Chang-Hung; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-三月-2012 | A Closed-Form Quantum "Dark Space" Model for Predicting the Electrostatic Integrity of Germanium MOSFETs With High-k Gate Dielectric | Wu, Yu-Sheng; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 七月-2016 | A Compact Subthreshold Model for Short-Channel Monolayer Transition Metal Dichalcogenide Field-Effect Transistors | You, Wei-Xiang; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-十月-2013 | Comparative Leakage Analysis of GeOI FinFET and Ge Bulk FinFET | Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-七月-2009 | A Comparative Study of Carrier Transport for Overlapped and Nonoverlapped Multiple-Gate SOI MOSFETs | Lee, Wei; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-三月-2011 | Comparison of 4T and 6T FinFET SRAM Cells for Subthreshold Operation Considering Variability-A Model-Based Approach | Fan, Ming-Long; Wu, Yu-Sheng; Hu, Vita Pi-Ho; Hsieh, Chien-Yu; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2011 | Comprehensive Analysis of UTB GeOI Logic Circuits and 6T SRAM Cells considering Variability and Temperature Sensitivity | Hu, Vita Pi-Ho; Fan, Ming-Long; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
