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Showing results 1 to 4 of 4
Issue DateTitleAuthor(s)
2001Compact layout rule extraction for latchup prevention in a 0.25-mu m shallow-trench-isolation silicided bulk CMOS processKer, MD; Lo, WY; Chen, TY; Tang, H; Chen, SS; Wang, MC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Apr-2004Electrostatic discharge protection under pad design for copper-low-K VLSI circuitsLee, JW; Li, YM; Chao, A; Tang, H; 友訊交大聯合研發中心; D Link NCTU Joint Res Ctr
2001Investigation on ESD robustness of CMOS devices in a 1.8-v 0.15-mu m partially-depleted SOI salicide CMOS technologyKer, MD; Hong, KK; Chen, TY; Tang, H; Huang, SC; Chen, SS; Huang, CT; Wang, MC; Loh, YT; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1998Novel input ESD protection circuit with substrate-triggering technique in a 0.25-mu m shallow-trench-isolation CMOS technologyKer, MD; Chen, TY; Wu, CY; Tang, H; Su, KC; Sun, SW; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
Showing results 1 to 4 of 4