瀏覽 的方式： 作者 Tu, SW
顯示 1 到 6 筆資料，總共 6 筆
| 公開日期 | 標題 | 作者 |
| 1-四月-2003 | Inductance modeling for on-chip interconnects | Tu, SW; Shen, WZ; Chang, YW; Chen, TC; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2002 | Inductance modeling for on-chip interconnects | Tu, SW; Shen, WZ; Chang, YW; Chen, TC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2004 | Layout techniques for on-chip interconnect inductance reduction | Tu, SW; Jou, JY; Chang, YW; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2005 | On-chip bus encoding for LC cross-talk reduction | Huang, JS; Tu, SW; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2005 | RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction | Tu, SW; Jou, JY; Chang, YW; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2004 | RLC effects on worst-case switching pattern for on-chip buses | Tu, SW; Jou, JY; Chang, YW; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
