瀏覽 的方式： 作者 Tung, SW
顯示 1 到 8 筆資料，總共 8 筆
| 公開日期 | 標題 | 作者 |
| 1-一月-2003 | Automatic interconnection rectification for SoC design verification based on the port order fault model | Wang, CY; Tung, SW; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2003 | An automatic interconnection rectification technique for SoC design integration | Wang, CY; Tung, SW; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-十月-2002 | An automorphic approach to verification pattern generation for SoC design verification using port-order fault model | Wang, CY; Tung, SW; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2001 | An improved AVPG algorithm for SoC design verification using port order fault model | Wang, CY; Tung, SW; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-九月-1998 | A logical fault model for library coherence checking | Tung, SW; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-四月-2002 | On automatic-verification pattern generation for SoC with port-order fault model | Wang, CY; Tung, SW; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2001 | On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault model | Wang, CY; Tung, SW; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2003 | SOC design integration by using automatic interconnection rectification | Wang, CY; Tung, SW; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
