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Showing results 1 to 6 of 6
Issue DateTitleAuthor(s)
2000Auger recombination enhanced hot carrier degradation in nMOSFETs with positive substrate biasChiang, LP; Tsai, CW; Wang, T; Liu, UC; Wang, MC; Hsia, LC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2001Compact layout rule extraction for latchup prevention in a 0.25-mu m shallow-trench-isolation silicided bulk CMOS processKer, MD; Lo, WY; Chen, TY; Tang, H; Chen, SS; Wang, MC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2001Investigation on ESD robustness of CMOS devices in a 1.8-v 0.15-mu m partially-depleted SOI salicide CMOS technologyKer, MD; Hong, KK; Chen, TY; Tang, H; Huang, SC; Chen, SS; Huang, CT; Wang, MC; Loh, YT; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2004A method for fabricating a superior oxide/nitride/oxide gate stackChang, TC; Yan, ST; Liu, PT; Wang, MC; Sze, SM; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2001Novel diode structures and ESD protection circuits in a 1.8-V 0.15-mu m partially-depleted SOI salicided CMOS processKer, MD; Hung, KK; Tang, HTH; Huang, SC; Chen, SS; Wang, MC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2000Valence-band tunneling enhanced hot carrier degradation in ultra-thin oxide nMOSFETsTsai, CW; Gu, SH; Chiang, LP; Wang, TH; Liu, YC; Huang, LS; Wang, MC; Hsia, LC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
Showing results 1 to 6 of 6