瀏覽 的方式： 作者 Wang, MC
顯示 1 到 6 筆資料，總共 6 筆
| 公開日期 | 標題 | 作者 |
| 2000 | Auger recombination enhanced hot carrier degradation in nMOSFETs with positive substrate bias | Chiang, LP; Tsai, CW; Wang, T; Liu, UC; Wang, MC; Hsia, LC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2001 | Compact layout rule extraction for latchup prevention in a 0.25-mu m shallow-trench-isolation silicided bulk CMOS process | Ker, MD; Lo, WY; Chen, TY; Tang, H; Chen, SS; Wang, MC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2001 | Investigation on ESD robustness of CMOS devices in a 1.8-v 0.15-mu m partially-depleted SOI salicide CMOS technology | Ker, MD; Hong, KK; Chen, TY; Tang, H; Huang, SC; Chen, SS; Huang, CT; Wang, MC; Loh, YT; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2004 | A method for fabricating a superior oxide/nitride/oxide gate stack | Chang, TC; Yan, ST; Liu, PT; Wang, MC; Sze, SM; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2001 | Novel diode structures and ESD protection circuits in a 1.8-V 0.15-mu m partially-depleted SOI salicided CMOS process | Ker, MD; Hung, KK; Tang, HTH; Huang, SC; Chen, SS; Wang, MC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2000 | Valence-band tunneling enhanced hot carrier degradation in ultra-thin oxide nMOSFETs | Tsai, CW; Gu, SH; Chiang, LP; Wang, TH; Liu, YC; Huang, LS; Wang, MC; Hsia, LC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
