瀏覽 的方式： 作者 Yu, Chien-Lin
顯示 1 到 4 筆資料，總共 4 筆
| 公開日期 | 標題 | 作者 |
| 1-一月-2017 | Investigation and Comparison of Design Space for Ultra-Thin-Body GeOI/SOI Negative Capacitance FETs | Lee, Ho-Pei; Yu, Chien-Lin; You, Wei-Xiang; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-六月-2019 | Investigation of Fin-Width Sensitivity of Threshold Voltage for InGaAs and Si Negative-Capacitance FinFETs Considering Quantum-Confinement Effect | Huang, Shih-En; Yu, Chien-Lin; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 1-一月-2017 | Theoretical Investigation of DIBL Characteristics for Scaled Tri-Gate InGaAs-OI n-MOSFETs Including Sensitivity to Process Variations | Wu, Shu-Hua; Yu, Chien-Lin; Yu, Chang-Hung; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics |
| 2016 | 超薄絕緣三五族金氧半場效電晶體與負電容場效電晶體之量子次臨界模型建立 | 余建霖; 蘇彬; Yu, Chien-Lin; Su, Pin; 電子研究所 |
