完整後設資料紀錄
DC 欄位語言
dc.contributor.author黃調元en_US
dc.contributor.authorHUANG TIAO-YUANen_US
dc.date.accessioned2014-12-13T10:51:16Z-
dc.date.available2014-12-13T10:51:16Z-
dc.date.issued2008en_US
dc.identifier.govdocNSC96-2221-E009-207-MY2zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/102619-
dc.identifier.urihttps://www.grb.gov.tw/search/planDetail?id=1621870&docId=277558en_US
dc.description.abstract本計畫是探討具有完全金屬矽化閘極之局部(單軸)形變矽通道之金氧半元件製作與 特性分析;局部形變是利用LPCVD 與PECVD 沉積氮化矽產生伸張應力及壓縮應力, 鎳金屬矽化則是沉積不同厚度比之鎳/複晶矽閘極以形成NiSi 與Ni-rich 相位之完全金屬 矽化閘極。本計畫中首度提出一種緩衝層結構概念,即在沉積氮化矽之前先成長一層薄 薄的緩衝層,薄的緩衝層能在不損失氮化矽產生之形變應力,卻能抵擋成長氮化矽過程 氫原子擴散進入通道區域,以提升元件可靠度。此外,亦將改變沉積之氣體流量、壓力、 溫度等直接最佳化氮化矽,使氮化矽具有高伸張或高壓縮應力,卻含有少量之氫含量。 完全金屬閘極製作中,將探討功函數調整,與不同相位之完全金屬矽化閘極技術。此外, 使用高劑量佈植As 於閘極,經RTA 後利用閘極膨脹來達伸張形變矽通道。最後結合上 述最佳化之成果製作於N 型與P 型金氧半元件中。本計畫亦將探討能階窄化現象、氫 的擴散路徑、固態溶解度效應及界面能態側向分佈等效應,並對元件做熱載子劣化及直 流與交流之負偏壓溫度不穩定性之可靠度分析。zh_TW
dc.description.abstractIn this project we plan to fabricate and investigate the characteristics of MOSFETs with FUSI gate and locally (uniaxially) strained Si channel. Local strain is induced by capping a SiN layer using a LPCVD or a PECVD system to result in tensile or compressive strain, respectively, in the channel. Different thickness ratio of Ni/poly-Si is deposited to form Ni-FUSI with NiSi or Ni-rich phase. In the project, for the first time, we propose the use of a buffer layer prior to the SiN capping to improve the device reliability performance. A thin buffer layer can potentially suppress the diffusion of hydrogen species into the channel region to improve device reliability without comprising the performance gain from the channel strain. Moreover, SiN film is optimized directly by adjusting the CVD conditions, including gas flow, pressure, and temperature. It is desired to deposit films with higher tensile (compressive) strain for NMOSFETs (PMOSFETs) but small amount of hydrogen species. We also investigate the adjustment of metal work-function using Ni-FUSI gate with different phase composition. Moreover, strain effect induced in a high-dose As-implanted gate will also be explored. Finally, the optimized results mentioned above are combined to fabricate the n-channel and p-channel MOSFETs. Band gap narrowing effect, hydrogen diffusion paths, solid solubility effect, and lateral distribution of interface states will be evaluated comprehensively in this project. Reliability issues are discussed by hot carrier stress, DC and AC NBTI stressing.en_US
dc.description.sponsorship行政院國家科學委員會zh_TW
dc.language.isozh_TWen_US
dc.subject局部形變矽zh_TW
dc.subject完全金屬矽化閘極zh_TW
dc.subject緩衝層zh_TW
dc.subject功函數調變zh_TW
dc.subject能階窄化zh_TW
dc.subject熱載子效應zh_TW
dc.subject負偏壓溫度不穩定性zh_TW
dc.subjectLocal strained Sien_US
dc.subjectFUSI gateen_US
dc.subjectBuffer layeren_US
dc.subjectWork function adjustingen_US
dc.subjectBandgap narrowingen_US
dc.subjectHot carrier stressen_US
dc.subjectNegative bias temperature instabilityen_US
dc.title具有形變通道與完全金屬矽化閘極之互補式金氧半電晶體的製造與分析zh_TW
dc.titleFabrication and Characterization of Strained-Channel CMOS Devices with FUSI Gateen_US
dc.typePlanen_US
dc.contributor.department國立交通大學電子工程學系及電子研究所zh_TW
顯示於類別:研究計畫