| Title: | 單晶片系統驗證之核心技術開發---子計畫四：單晶片系統設計流程之實體驗證(III) Physical Verification for SoC Design Flow(III) |
| Authors: | 江蕙如 Jiang Iris Hui-Ru 國立交通大學電子工程學系及電子研究所 |
| Issue Date: | 2007 |
| Gov't Doc #: | NSC96-2220-E009-010 |
| URI: | http://hdl.handle.net/11536/102948 https://www.grb.gov.tw/search/planDetail?id=1467025&docId=263108 |
| Appears in Collections: | Research Plans |
