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dc.contributor.author許騰尹en_US
dc.contributor.author賴煒棋en_US
dc.date.accessioned2014-12-16T06:12:09Z-
dc.date.available2014-12-16T06:12:09Z-
dc.date.issued2012-05-01en_US
dc.identifier.govdocG06F007/548zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/103468-
dc.description.abstract本發明提供一種低延遲時間之餘切硬體結構及其計算方法,其包括二對照表、一減法器、一正負比較器、一數値比較器、及一位移編碼器,本發明將座標系統分成複數等份並對應對照表,第一對照表做對數之轉換,以將除法器改為使用減法器,而第二對照表整合指數及餘切角度,可將減法器之結果轉換成餘切之角度��,接著依據位移編碼器可將角度��移到正確的角度。zh_TW
dc.language.isozh_TWen_US
dc.title低延遲時間之餘切硬體結構及其計算方法zh_TW
dc.typePatentsen_US
dc.citation.patentcountryTWNzh_TW
dc.citation.patentnumber201218071zh_TW
Appears in Collections:Patents


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