完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.author | Shirota Riichiro | en_US |
| dc.contributor.author | Watanabe Hiroshi | en_US |
| dc.date.accessioned | 2014-12-16T06:15:02Z | - |
| dc.date.available | 2014-12-16T06:15:02Z | - |
| dc.date.issued | 2013-01-03 | en_US |
| dc.identifier.govdoc | H01L029/788 | zh_TW |
| dc.identifier.govdoc | G11C016/02 | zh_TW |
| dc.identifier.uri | http://hdl.handle.net/11536/105092 | - |
| dc.description.abstract | An application circuit and an operation method of a semiconductor device are provided. A leakage current among a control gate diffusion layer, a source diffusion layer and a drain is reduced by adjusting biases applied on a double well region, so as to reduce the product cost and improve the accuracy of a battery-less electronic timer that uses the semiconductor device. | zh_TW |
| dc.language.iso | zh_TW | en_US |
| dc.title | APPLICATION CIRCUIT AND OPERATION METHOD OF SEMICONDUCTOR DEVICE | zh_TW |
| dc.type | Patents | en_US |
| dc.citation.patentcountry | USA | zh_TW |
| dc.citation.patentnumber | 20130003466 | zh_TW |
| 顯示於類別: | 專利資料 | |

