Fabrication and Characterization of Pi-Gate Poly-Si Junctionless and Inversion Mode Fin-FETs for 3-D IC Applications

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DC Field	Value	Language
dc.contributor.author	Hsieh, Don-Ru	en_US
dc.contributor.author	Lin, Jer-Yi	en_US
dc.contributor.author	Kuo, Po-Yi	en_US
dc.contributor.author	Chao, Tien-Sheng	en_US
dc.date.accessioned	2017-04-21T06:48:46Z	-
dc.date.available	2017-04-21T06:48:46Z	-
dc.date.issued	2016	en_US
dc.identifier.isbn	978-1-5090-0726-4	en_US
dc.identifier.uri	http://hdl.handle.net/11536/134680	-
dc.description.abstract	In this paper, the Pi-gate (PG) poly-Si junctionless (JL) and inversion mode (IM) Fin-FETs have been successfully fabricated and demonstrated without using costly lithography technique. The PG JL Fin-FETs show excellent electrical performance in terms of low gate overdrive voltage, extremely near-ideal subthreshold swing (S.S.) similar to 68 mV/dec., steep average subthreshold swing (A.S.S.) similar to 73 mV/dec., smaller drain induced barrier lowing (DIBL) similar to 9 mV/V, and higher I-on/I-off ratio similar to 1.1 x 10(8) (V-D = 1 V).	en_US
dc.language.iso	en_US	en_US
dc.title	Fabrication and Characterization of Pi-Gate Poly-Si Junctionless and Inversion Mode Fin-FETs for 3-D IC Applications	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2016 IEEE SILICON NANOELECTRONICS WORKSHOP (SNW)	en_US
dc.citation.spage	110	en_US
dc.citation.epage	111	en_US
dc.contributor.department	電子物理學系	zh_TW
dc.contributor.department	Department of Electrophysics	en_US
dc.identifier.wosnumber	WOS:000391250500046	en_US
dc.citation.woscount	0	en_US
Appears in Collections:	Conferences Paper