完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.author | Shih, Che-Hua | en_US |
| dc.contributor.author | Yen, Chia-Chih | en_US |
| dc.contributor.author | Lin, Shen-Tien | en_US |
| dc.contributor.author | Lin, Hermes | en_US |
| dc.contributor.author | Jou, Jing-Yang | en_US |
| dc.date.accessioned | 2017-04-21T06:50:05Z | - |
| dc.date.available | 2017-04-21T06:50:05Z | - |
| dc.date.issued | 2011 | en_US |
| dc.identifier.isbn | 978-1-4244-8499-7 | en_US |
| dc.identifier.uri | http://hdl.handle.net/11536/134794 | - |
| dc.description.abstract | Accurate peak power measurement requires detailed switching and delay information for each signal over the entire simulation. Performing a full signal dump and power calculation for a long simulation run usually spends a large amount of time and disk space. In this paper, we propose an Essential-signal-based methodology which only performs power analysis over a small subset of the original simulation but still acquires the true peak power value. Experimental results show that the proposed methodology significantly decreases both time (about 18 X speedup) and disk space usage (about 87% reduction) against the traditional power analysis flow. | en_US |
| dc.language.iso | en_US | en_US |
| dc.title | Accelerating Dynamic Peak Power Analysis Using An Essential-Signal-Based Methodology | en_US |
| dc.type | Proceedings Paper | en_US |
| dc.identifier.journal | 2011 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT) | en_US |
| dc.citation.spage | 140 | en_US |
| dc.citation.epage | 144 | en_US |
| dc.contributor.department | 交大名義發表 | zh_TW |
| dc.contributor.department | National Chiao Tung University | en_US |
| dc.identifier.wosnumber | WOS:000300488600027 | en_US |
| dc.citation.woscount | 0 | en_US |
| 顯示於類別: | 會議論文 | |

