Title: | A new Schmitt trigger circuit in a 0.13-mu m 1/2.5-V CMOS process to receive 3.3-V input signals |
Authors: | Chen, SL Ker, MD 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
Keywords: | gate-oxide reliability;input-output (I/O);mixed-voltage interface;Schmitt trigger |
Issue Date: | 1-Jul-2005 |
Abstract: | A new Schmitt trigger circuit, which is implemented by low-voltage devices to receive the high-voltage input signals without gate-oxide reliability problem, is proposed. The new proposed circuit, which can be operated in a 3.3-V signal environment without suffering high-voltage gate-oxide overstress, has been fabricated in a 0.13-mu m 1/2.5-V 1P8M CMOS process. The experimental results have confirmed that the measured transition threshold voltages of the new proposed Schmitt trigger circuit are about 1 and 2.5 V, respectively. The new proposed Schmitt trigger circuit is suitable for mixed-voltage input-output interfaces to receive input signals and reject input noise. |
URI: | http://dx.doi.org/10.1109/TCSII.2005.850409 http://hdl.handle.net/11536/13511 |
ISSN: | 1057-7130 |
DOI: | 10.1109/TCSII.2005.850409 |
Journal: | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS |
Volume: | 52 |
Issue: | 7 |
Begin Page: | 361 |
End Page: | 365 |
Appears in Collections: | Articles |
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