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國立陽明交通大學機構典藏
學術出版
會議論文
標題:
High holding voltage segmentation stacking silicon-controlled-rectifier structure with field implant as body ties blocking layer
作者:
Yen, Shiang-Shiou
Cheng, Chun-Hu
Lan, Yu-Pin
Chiu, Yu-Chien
Fan, Chia-Chi
Hsu, Hsiao-Hsuan
Chang, Shao-Chin
Jiang, Zhe-Wei
Hung, Li-Yue
Tsai, Chi-Chung
Chang, Chun-Yen
電子工程學系及電子研究所
友訊交大聯合研發中心
Department of Electronics Engineering and Institute of Electronics
D Link NCTU Joint Res Ctr
公開日期:
四月-2016
摘要:
High electrostatic discharge (ESD) protection robustness and good transient-induced latchup immunity are two important issues for high voltage integrate circuit application. In this study, we report a high-voltage-n-type-field (HVNF) implantation to act as the body ties blocking layer in segmented topology silicon-controlled-rectifier (SCR) structure in 0.11 mu m 32 V high voltage process. This body ties blocking layer eliminate the elevated triggered voltage in segmented technique. Using a large resistance as shunt resistor in resistor assisted triggered SCRs stacking structure, the double snapback phenomenon is eliminate. The series SCR could be decoupled a sufficient voltage drop to turned-on when a very low current flow through the shunt resistor. The holding voltage and the failure current of 22 V and 3.4 A are achieved in the best condition of segmented topology SCR stacking structure, respectively. It improves the latchup immunity at high voltage ICs application. On the other hand, the triggered voltage almost keep the same value which is identical to SCR single cell without using segmented topology. (C) 2016 The Japan Society of Applied Physics
URI:
http://dx.doi.org/10.7567/JJAP.55.04ER10
http://hdl.handle.net/11536/135212
ISSN:
0021-4922
DOI:
10.7567/JJAP.55.04ER10
期刊:
JAPANESE JOURNAL OF APPLIED PHYSICS
Volume:
55
Issue:
4
顯示於類別:
會議論文
IR@NYCU
CrossRef
High holding voltage segmentation stacking silicon-controlled-rectifier structure with field implant as body ties blocking layer / Yen, Shiang-Shiou;Cheng, Chun-Hu;Lan, Yu-Pin;Chiu, Yu-Chien;Fan, Chia-Chi
高壓BCD製程之靜電放電防護元件設計與實現 / 許哲綸;Hsu, Che-Lun;柯明道;Ker, Ming-Dou
ESD Protection Design With Stacked High-Holding-Voltage SCR for High-Voltage Pins in a Battery-Monitoring IC / Dai, Chia-Tsen;Ker, Ming-Dou
SCR device with dynamic holding voltage for on-chip ESD protection in a 0.25-mu m fully salicided CMOS process / Ker, MD;Chen, ZP
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