Title: JAIP-MP: A Four-Core Java Application Processor
Authors: Tsai, Chun-Jen
Wu, Tsung-Han
Su, Hung-Cheng
資訊工程學系
Department of Computer Science
Keywords: Java processor;multi-core;embedded SoC;hardwired multi-threading;cache coherence
Issue Date: 2015
Abstract: In this paper, we present the design of a four-core Java application processor, JAIP-MP. Each processor core in JAIP-MP is a hardwired Java core that supports dynamic class loading, two-fold bytecode execution, object-oriented dynamic resolution, method and object caching, Java exception handling, and temporal multithreading. For JAIP-MP, a global load-balancing task manager is used to evenly distribute Java threads among the local task queues of every processor cores. In addition, a data coherence controller is designed to enforce coherence across all data caches and to perform synchronization operations among Java threads of all processor cores. Since thread management and synchronization mechanisms are completely implemented in hardware, the single-core multi-tasking performance of JAIP-MP is much higher than that of a software-based VM running on a traditional OS kernel such as Linux. For execution of multithreading applications, the speedup of a four-core JAIP-MP system can be up to 3.69 times faster than a single-core JAIP system, tested using the JemBench parallel benchmark programs.
URI: http://hdl.handle.net/11536/135936
ISBN: 978-1-4673-9140-5
Journal: 2015 IFIP/IEEE INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION (VLSI-SOC)
Begin Page: 189
End Page: 194
Appears in Collections:Conferences Paper