Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Wang, Yun-Ting | en_US |
dc.contributor.author | Lee, Jia-Ying | en_US |
dc.contributor.author | Lai, Bo-Cheng Charles | en_US |
dc.date.accessioned | 2017-04-21T06:49:33Z | - |
dc.date.available | 2017-04-21T06:49:33Z | - |
dc.date.issued | 2015 | en_US |
dc.identifier.isbn | 978-1-4799-8058-1 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/136316 | - |
dc.description.abstract | GPUs have emerged as popular throughput computing platforms due to the massively parallel computing capability and low cost. To attain further performance enhancement beyond single GPU, there is a growing interest in exploiting systems with multiple GPUs. Attaining superior performance in a multi-GPU system involves three main design challenges, namely load balance, memory utilization, and data transfer. Imbalanced loading across a system could cause idling of GPUs while poor data reuse would trigger excessive memory accesses. The inefficient data transfer between a host and a device becomes a considerable performance overhead during high throughput computing. This paper aims at addressing the above design issues by proposing a Computation and Communication Aware task graph Scheduling (CCAS) for multi-GPU systems. The proposed scheduling approach (CCAS) adopts an effective heuristic algorithm that considers both data reuse and load balance in a multi-GPU system. The data transfer overhead is hidden by extensively overlapping computation and data communication. The experimental results of the proposed CCAS have demonstrated an average of 22.15% performance enhancement when compared with a previous work. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | GPUs | en_US |
dc.subject | Scheduling | en_US |
dc.subject | Task Graph | en_US |
dc.title | Computation and Communication Aware Task Graph Scheduling on Multi-GPU Systems | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2015 IEEE INTERNATIONAL CONFERENCE ON DIGITAL SIGNAL PROCESSING (DSP) | en_US |
dc.citation.spage | 115 | en_US |
dc.citation.epage | 119 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000380506600023 | en_US |
dc.citation.woscount | 0 | en_US |
Appears in Collections: | Conferences Paper |