完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Liao, Chien-Hui | en_US |
dc.contributor.author | Wen, Charles H. -P. | en_US |
dc.date.accessioned | 2018-08-21T05:53:14Z | - |
dc.date.available | 2018-08-21T05:53:14Z | - |
dc.date.issued | 2017-12-01 | en_US |
dc.identifier.issn | 1745-1337 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1587/transfun.E100.A.2901 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/144426 | - |
dc.description.abstract | Hotspots occur frequently in 3D multi-core processors (3D-MCPs), and they may adversely impact both the reliability and lifetime of a system. We present a new thermally constrained task scheduler based on a thermal-pattern-aware voltage assignment (TPAVA) to reduce hotspots in and optimize the performance of 3D-MCPs. By analyzing temperature profiles of different voltage assignments, TPAVA pre-emptively assigns different initial operating-voltage levels to cores for reducing temperature increase in 3D-MCPs. The proposed task scheduler consists of an on-line allocation strategy and a new voltage-scaling strategy. In particular, the proposed on-line allocation strategy uses the temperature-variation rates of the cores and takes into two important thermal behaviors of 3D-MCPs that can effectively minimize occurrences of hotspots in both thermally homogeneous and heterogeneous 3D-MCPs. Furthermore, a new vertical-grouping voltage scaling (VGVS) strategy that considers thermal correlation in 3D-MCPs is used to handle thermal emergencies. Experimental results indicate that, when compared to a previous online thermally constrained task scheduler, the proposed task scheduler can reduce hotspot occurrences by approximately 66% (71%) and improve throughput by approximately 8% (2%) in thermally homogeneous (heterogeneous) 3D-MCPs. These results indicate that the proposed task scheduler is an effective technique for suppressing hotspot occurrences and optimizing throughput for 3D-MCPs subject to thermal constraints. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | on-line task scheduler | en_US |
dc.subject | 3D multi-core processors | en_US |
dc.subject | thermally homogeneous and heterogeneous floorplans | en_US |
dc.subject | hotspots | en_US |
dc.subject | voltage assignment | en_US |
dc.title | An Online Thermal-Pattern-Aware Task Scheduler in 3D Multi-Core Processors | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1587/transfun.E100.A.2901 | en_US |
dc.identifier.journal | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES | en_US |
dc.citation.volume | E100A | en_US |
dc.citation.spage | 2901 | en_US |
dc.citation.epage | 2910 | en_US |
dc.contributor.department | 電機工程學系 | zh_TW |
dc.contributor.department | 電信工程研究所 | zh_TW |
dc.contributor.department | Department of Electrical and Computer Engineering | en_US |
dc.contributor.department | Institute of Communications Engineering | en_US |
dc.identifier.wosnumber | WOS:000423266000041 | en_US |
顯示於類別: | 期刊論文 |