Title: DPLL for Phase Noise Cancellation in Ring Oscillator-Based Quadrature Receivers
Authors: Chen, Zuow-Zun
Kuan, Yen-Cheng
Li, Yilei
Hu, Boyu
Wong, Chien-Heng
Chang, Mau-Chung Frank
交大名義發表
國際半導體學院
National Chiao Tung University
International College of Semiconductor Technology
Keywords: Digital phase-locked loop (DPLL);frequency synthesizer;phase noise cancellation;radio receiver;ring oscillator (RO);sub-sampling time-to-digital converter (TDC)
Issue Date: 1-Apr-2017
Abstract: In this paper, a low overhead phase noise cancellation technique for ring oscillator (RO)-based quadrature receivers is presented. The proposed technique operates in background and extracts RO phase noise as well as supply-induced phase noise from the digital phase-locked loop. The obtained phase noise information is then used to restore the randomly rotated baseband signal in digital domain. A receiver prototype is fabricated in standard 65-nm CMOS technology. It demonstrates a phase noise reduction from -88 to -109 dBc/Hz at 1-MHz offset and an integrated phase noise reduction from -16.8 to -34.6 dBc when operating at 2.4 GHz.
URI: http://dx.doi.org/10.1109/JSSC.2017.2647925
http://hdl.handle.net/11536/145344
ISSN: 0018-9200
DOI: 10.1109/JSSC.2017.2647925
Journal: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 52
Begin Page: 1134
End Page: 1143
Appears in Collections:Articles