Scaling of Gate Dielectric on Ge Substrate

Abstract

Scaling of Hf-based and Zr-based gate dielectric stack on Ge is investigated. Effects of dielectric thickness and thermal budget on the MOS device characteristics are studied. Tradeoff among effective oxide thickness (EOT), leakage current density (J(G)), interface state density (D-it), and hysteresis are observed and discussed. With the same HfO2 and ZrO2 thickness, the ZrO2 samples exhibit lower D-it and smaller hysteresis but slightly higher J(G). The crystallized ZrO2 exhibits the best J(G)-EOT performance. However, as the EOT becomes thinner than 0.8 nm, it is hard to lower D-it to 1x10 (12) eV(-1)cm(-2). According to these results, novel techniques for Ge surface passivation and ZrO2 crystallization are required.