A 19.1% PAE, 22.4-dBm 53-GHz Parallel Power Combining Power Amplifier with Stacked-FET Techniques in 90-nm CMOS

Title:	A 19.1% PAE, 22.4-dBm 53-GHz Parallel Power Combining Power Amplifier with Stacked-FET Techniques in 90-nm CMOS
Authors:	Sun, Wei-Che Kuo, Chien-Nan 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics
Keywords:	amplifiers;CMOS;millimeter wave;power amplifiers;power combiner;transformers;stacked transistors
Issue Date:	1-Jan-2019
Abstract:	A two-stage fully integrated 53-GHz stacked-FET power amplifier (PA) is implemented in 90-nm bulk CMOS. The output stage is optimized to achieve high output power while maintaining high power added efficiency (PAE). The complete PA achieves a measured saturated output power of 22.4 dBm and the 19.1% PAE at 2.4 V supply. It has -3 dB bandwidth of 8.8 GHz.
URI:	http://hdl.handle.net/11536/153306
ISBN:	978-1-7281-1309-8
ISSN:	0149-645X
Journal:	2019 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM (IMS)
Begin Page:	327
End Page:	330
Appears in Collections:	Conferences Paper