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dc.contributor.authorLin, Yu-Minen_US
dc.contributor.authorWu, Sheng-Tsaien_US
dc.contributor.authorShen, Wen-Weien_US
dc.contributor.authorHuang, Shin-Yien_US
dc.contributor.authorKuo, Tzu-Yingen_US
dc.contributor.authorLin, Ang-Yingen_US
dc.contributor.authorChang, Tao-Chihen_US
dc.contributor.authorChang, Hsiang-Hungen_US
dc.contributor.authorLee, Shu-Manen_US
dc.contributor.authorLee, Chia-Hsinen_US
dc.contributor.authorSu, Jayen_US
dc.contributor.authorLiu, Xiaoen_US
dc.contributor.authorWu, Qien_US
dc.contributor.authorChen, Kuan-Nengen_US
dc.date.accessioned2020-07-01T05:21:48Z-
dc.date.available2020-07-01T05:21:48Z-
dc.date.issued2018-01-01en_US
dc.identifier.isbn978-1-5386-4998-5en_US
dc.identifier.issn0569-5503en_US
dc.identifier.urihttp://dx.doi.org/10.1109/ECTC.2018.00060en_US
dc.identifier.urihttp://hdl.handle.net/11536/154475-
dc.description.abstractFan-out wafer-level packaging (FOWLP), a new heterogeneous integration technology, is gradually becoming an attractive solution. Compared with conventional 2.5D/3D IC structures, fan-out WLP does not use a costly interposer element and can have a thin, high-density, and low-cost IC packaging. In this study, a novel fan-out WLP with RDL-first method is demonstrated. Finite element method was used to optimize the warpage control of a reconstituted wafer and to identify the material properties and fabrication for the FOWLP. Calculation results were applied in the design of the test vehicle. Reliability testing of each component level was performed with different techniques such as temperature cycling test (TCT), high temperature storage (HTS) and thermal humidity storage test (THST). The demonstration of RDL-first WLP technology without interposer proves that it has excellent potential for heterogeneous integration applications.en_US
dc.language.isoen_USen_US
dc.subjectFan-out wafer level packagingen_US
dc.subjectFO-WLPen_US
dc.subjectProcess developmenten_US
dc.subjectFinite element method (FEM)en_US
dc.subjectreliability testen_US
dc.titleAn RDL-First Fan-out Wafer-level Package for Heterogeneous Integration Applicationsen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1109/ECTC.2018.00060en_US
dc.identifier.journal2018 IEEE 68TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2018)en_US
dc.citation.spage349en_US
dc.citation.epage354en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000514675100053en_US
dc.citation.woscount1en_US
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