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dc.contributor.authorLin, SPen_US
dc.contributor.authorLee, CLen_US
dc.contributor.authorChen, JEen_US
dc.date.accessioned2014-12-08T15:25:18Z-
dc.date.available2014-12-08T15:25:18Z-
dc.date.issued2005en_US
dc.identifier.isbn0-7695-2481-8en_US
dc.identifier.issn1081-7735en_US
dc.identifier.urihttp://hdl.handle.net/11536/17688-
dc.description.abstractapplication time. In this paper, we propose and demonstrate an Adaptive Encoding scheme to reduce the test volume and test time for SoC scan test. The scheme, instead of handling test data themselves, encodes them in "packets" according to difference hits of two consecutive test patterns. A decoder machine is designed to decode the compressed data and a repeat filling mechanism from the ATE is adopted to eliminate the synchronization problem. It supports variable block size and is flexible in encoding multi-core test patterns; therefore, the proposed method is effective in SoC scan test. Experimental results show that on average the scheme achieves 73% reduction in test data and more than 16 times of speedup in test application time.en_US
dc.language.isoen_USen_US
dc.titleAdaptive encoding scheme for test volume/time reduction in SoC scan testingen_US
dc.typeProceedings Paperen_US
dc.identifier.journal14TH ASIAN TEST SYMPOSIUM, PROCEEDINGSen_US
dc.citation.spage324en_US
dc.citation.epage329en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000236209400054-
顯示於類別:會議論文