Title: | Impact of Gate-Oxide Breakdown on Power-Gated SRAM |
Authors: | Yang, Hao-I Chuang, Ching-Te Hwang, Wei 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
Keywords: | gate-oxide breakdown;power gating technology;SRAM |
Issue Date: | 2009 |
Abstract: | This paper presents a detailed analysis on the impacts of various gate-oxide breakdown (BD) paths in column-based header- and footer-gated SRAMs. It is shown that with gate-oxide BD, the RSNM (Read Static Noise Margin) degrades, while the WM (Write Margin) improves in general. The effects of gate-to-source BD of cell transistors are shown to confine to the individual cell, while multiple cells suffering cell transistor drain-to-drain BD in a column could cumulatively affect VVDD (header structure) or VVSS (footer structure), thus influencing other cells in the same column. In particular, we show that the gate-oxide BD of the power-switches have server and even detrimental effects on the margin, stability, and performance of the SRAM array |
URI: | http://hdl.handle.net/11536/17702 |
ISBN: | 978-1-4244-2933-2 |
Journal: | 2009 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGS |
Begin Page: | 93 |
End Page: | 96 |
Appears in Collections: | Conferences Paper |