Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chen, JS | en_US |
dc.contributor.author | Ker, MD | en_US |
dc.date.accessioned | 2014-12-08T15:25:22Z | - |
dc.date.available | 2014-12-08T15:25:22Z | - |
dc.date.issued | 2005 | en_US |
dc.identifier.isbn | 0-7803-8803-8 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/17749 | - |
dc.description.abstract | The effects of the gate-oxide reliability of MOSFETs on operational amplifiers were investigated with the two-stage and folded-cascode structures in a 130-nm low-voltage CMOS process. The tested operating conditions include unity-gain buffer (close-loop configuration) and comparator (open-loop configuration) under different input frequencies and signals. After overstress, the small-signal parameters, such as small-signal gain, unity-gain frequency, and phase margin, were measured to verify the impact of gate-oxide reliability on circuit performances of the operational amplifier. The gate-oxide reliability can be improved by the stacked configuration in the operational amplifier with folded-cascode structure. A simple equivalent device model of gate-oxide reliability for CMOS devices in analog circuits was investigated and simulated. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Impact of MOSFET gate-oxide reliability on CMOS operational amplifiers in a 130-nm low-voltage CMOS process | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2005 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 43RD ANNUAL | en_US |
dc.citation.spage | 423 | en_US |
dc.citation.epage | 430 | en_US |
dc.contributor.department | 電機學院 | zh_TW |
dc.contributor.department | College of Electrical and Computer Engineering | en_US |
dc.identifier.wosnumber | WOS:000230058000070 | - |
Appears in Collections: | Conferences Paper |