Title: A new dynamic scaling FFT processor
Authors: Lin, YW
Lee, CY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
Issue Date: 2004
Abstract: A new FFT processor with radix-8 algorithm and novel matrix buffer is presented in this paper. About 64 K bit memory can be saved in 8 K-point FFT by new dynamic scaling approach. Moreover, with data scheduling and prefetched buffering, single-port memory can be adopted in our FFT processor. A test chip for 8 K mode DVB-T system has been designed and fabricated using 0.18 mu m CMOS process with core area of 4.84mm(2) and consumes only 25.2 mW at 20 MHz.
URI: http://hdl.handle.net/11536/18311
ISBN: 0-7803-8660-4
Journal: PROCEEDINGS OF THE 2004 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1 AND 2: SOC DESIGN FOR UBIQUITOUS INFORMATION TECHNOLOGY
Begin Page: 449
End Page: 452
Appears in Collections:Conferences Paper