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dc.contributor.authorTsai, HWen_US
dc.contributor.authorChiang, PYen_US
dc.contributor.authorChung, SSen_US
dc.contributor.authorKuo, DSen_US
dc.contributor.authorLiang, MSen_US
dc.date.accessioned2014-12-08T15:26:10Z-
dc.date.available2014-12-08T15:26:10Z-
dc.date.issued2003en_US
dc.identifier.isbn0-7803-7765-6en_US
dc.identifier.urihttp://hdl.handle.net/11536/18558-
dc.identifier.urihttp://dx.doi.org/10.1109/VTSA.2003.1252545en_US
dc.description.abstractIn this paper, we proposed a simple approach for designing reliable and high performance p-channel Flash EEPROM cell from the floating-gate engineering point of view. In other words, a p-type doped floating gate used in a p-channel flash cell can achieve this goal. Results show that the programming speed, gate/drain disturb, read lifetime, and data retention in p-type floating-gate cell are much better than those of n-type floating-gate cell; except that p-type floating-gate cell has slower erasing speed. These results can be used as a guideline for designers to choose.en_US
dc.language.isoen_USen_US
dc.titleThe performance and reliability enhancement of ETOX P-channel flash EEPROM cell with P-doped floating-gateen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1109/VTSA.2003.1252545en_US
dc.identifier.journal2003 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERSen_US
dc.citation.spage36en_US
dc.citation.epage39en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000189391000010-
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